In memory modules it is necessary to decode received addresses for the selection of individual memory cells in the memory modules. For a change of these addresses, intermediate conditions can occur, wherein two or more memory cells are simultaneously addressed particularly for slow or mutually shifted switching edges of the address signals. This can result in mutual overwriting of the memory cells and, thus, to a loss of data. This problem in the prior art particularly occurs in high-speed memories, where uncertainties in the timing of the address signals become especially significant with reference to the internal switching times of the memory modules.
One known solution used with dynamic memories is to inhibit the address decoders with an additional address decoder enable signal until the address signals are received at the decoders in a stable fashion. Only then is the decoding enabled, so that only one decoder can supply a selection signal in response to the stable address signals.